例句與造句

1. optimal jamming of fh synchronous signals
   跳頻同步信號的最佳干擾
2. measuring source selected from ch1 or ch2 as synchronous signal sources
   測量感度：大于2格量測源選擇來自ch1或ch2之同步信號
3. the synchronous signal of mc1311 cmos camera is shaped by monostable trigger 74ls221
   使用單穩(wěn)態(tài)觸發(fā)器74ls221對送給mc1311cmos攝像機的同步信號進行整形。
4. single arm7 couldn ’ t supply synchronous signals, so test system was developed with cpld and arm7
   使用單一的arm7系統(tǒng)不能設(shè)計出完全同步的信號,所以采用cpld和arm7系統(tǒng)共同完成測試工作。
5. and the 1pps of the gps receiver is used as the synchronous signal and reference to ensure that the messured phasor of generator is the same reference
   采用gps的秒脈沖作為同步參考基準，從而保證了所測的各發(fā)電機的相角具有相同的參考基準。
6. It's difficult to find synchronous signals in a sentence. 用synchronous signals造句挺難的
7. digital signal processor ( dsp ) was used as the microcontroller of the daq card, and synchronous a / d converters were used to collect synchronous signals
   該數(shù)據(jù)采集卡以數(shù)字信號處理器(dsp)為主控制器，結(jié)合同步模數(shù)轉(zhuǎn)換器(adc)實現(xiàn)了多通道同步采集的功能。
8. the fault diagnosis system includes four parts : sampling and insulation of the synchronous signal, sampling of the voltage waveform of the rectifier, logic pre-processing and dft analysis, display and alarm circuit
   故障診斷系統(tǒng)主要包括同步信號的取樣與隔離、整流電壓的采樣、邏輯預處理及dft分析，診斷顯示報警電路等四部分。
9. meanwhile, a synchronous signal is generated to be the start signal of the high speed snapshot . in this case, the effective length of the film is increased enormously, which means that the resolution of the camera may be improved at the same rotating speed
   而且在測速的同時產(chǎn)生了一個高精度的同步信號作為高速攝影的觸發(fā)信號源,使得用于記錄信息的膠片的有效使用長度得到了很大的提高,這就意味著轉(zhuǎn)鏡相機的時間分辨率在相同的轉(zhuǎn)速下得到了提高。
10. the second, the main work in the paper is discussed . they are include : the theory and character of electromagnetic leaking from a computer; the theory of accumulation mean filter and pectination filter; the analysis of synchronous signal precision, at 10-12 second level, for stably intercepting; the technology requirement of receiver and data acquisition board for clearly displaying the images recovered from the intercepted data
    本文從計算機視頻電磁泄漏和數(shù)字濾波器兩方面的基本理論出發(fā)，詳細論述了計算機視頻信息電磁泄漏的原理及特點，指出視頻泄漏信息的頻譜是以行頻為周期的譜線；分析了重加濾波器和梳狀濾波器的性能；分析了視頻泄漏信息截獲的條件；推導出穩(wěn)定截獲視頻泄漏信息需要對同步信號的精度控制在皮秒級；論述了清晰再現(xiàn)對接收機和數(shù)據(jù)采集卡的技術(shù)要求。
11. the input data of the multiplexing adopts 8 channels with the speed of 2mb / s, and those of the last two channels are " 0 " and " 1 " respectively, in order to improve the transimision effeciency and deminish the complexity of encode and electronic circuit concerned, furthermore, it makes the synchronous signal acquisition more easier
    數(shù)字復接中采用八路2m口數(shù)據(jù)輸入，其中后兩路采用直接輸入“0”碼或“1”碼的方法，提高了信息傳輸?shù)挠行裕阌谔崛酱a，降低了編譯碼過程的復雜性，同時也降低了系統(tǒng)的電路復雜程度。
12. software includes designing of the dsp initialization files, sampling and processing program of the synchronous signal, sampling and logic pre-processing program of the rectifier voltage, program of fault diagnosis and location, display and alarm program, delay and isr program
    軟件部分主要包括：dsp初始化程序的設(shè)計、同步信號的獲取及處理程序、整流電壓的采樣和邏輯預處理程序、故障診斷及定位算法，顯示和報警程序及延時中斷服務(wù)程西安理工大學碩士學位論文序等。
13. the subject has mainly finished designing and debugging software and hardware of a / d decode module, fpga video processing module, video data frame deposit module, base clock produce module, d / a encode module, i2c bus control module, etc . a / d decode module gathers analog tv signals and realize video decode; fpga video processing module deals with the data after decoding and produces systematic logic control signal; video data frame deposit module offers the buffering area to a large n umber of high-speed video data; base clock produce module through input basic video signal offers system accurate relevant synchronous signal; under control of video processing module d / a decode module convert digital video data into compound tv signal which can be shown in tv directly; i2c bus control module is used to initialize the chip of system by simulating i * c bus timing
    本課題主要完成了ad解碼模塊、fpga視頻處理模塊、視頻數(shù)據(jù)幀存模塊、基準時鐘產(chǎn)生模塊、da編碼模塊、i~2c總線控制模塊等部分軟、硬件設(shè)計及調(diào)試。其中ad解碼模塊采集模擬電視信號實現(xiàn)視頻解碼；fpga視頻處理模塊對解碼后的數(shù)據(jù)進行去噪處理的同時還負責系統(tǒng)的邏輯控制；視頻數(shù)據(jù)幀存模塊為大量高速的視頻數(shù)據(jù)提供緩沖區(qū)；基準時鐘產(chǎn)生模塊通過輸入基準視頻信號為系統(tǒng)提供精確的相關(guān)同步信號；da編碼模塊在視頻處理模塊的控制下把數(shù)字視頻數(shù)據(jù)轉(zhuǎn)換成復合電視信號供顯示用：i~2c總線控制模塊模擬i~2c總線時序?qū)崿F(xiàn)對系統(tǒng)中編、解碼芯片的初始化。